Gratz, collaborators’ computer architecture paper selected as top pick in 2018

Dr. Paul Gratz, associate professor in the Department of Electrical and Computer Engineering at Texas A&M University, was recognized for his work in the paper titled “Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock Freedom.” The paper was selected as a top pick of all computer architecture papers published in 2018 by the Institute of Electrical and Electronics Engineers (IEEE) Micro publication.

Along with Gratz, Aniruddh Ramrakhyani and Tushar Krishna from the Georgia Institute of Technology were co-authors of this paper. In order for a paper to be chosen as a top pick it must first be accepted in a major computer architecture conference, then it is submitted for consideration. Out of 123 top pick submissions in 2018, their paper was one of the 12 awarded. IEEE Micro will publish the “Top Picks from the Computer Architecture Conferences” as its May/June 2019 issue.

One of the most fundamental design challenges in any high-performance computing or on-chip network are deadlocks. Deadlocks are circular resource dependencies within the network that prevent forward progress. They can be thought of in terms of a traffic jam that cannot resolve itself. Gratz explained that once a deadlock is formed without a resolution mechanism, it cannot ever resolve until the part is reset. Deadlocks are a design flaw that can break chips making the part useless if not caught early and prevented in the design stage. 

“The traditional approaches to solve them are very expensive either in terms of performance lost or resources wasted to prevent them,” Gratz said. “Our work means that the problem can be solved with much less resource consumption making processor chips less expensive, perform better and lower energy consumption.”

In their paper, Gratz and his collaborators challenge the theoretical notion of viewing deadlocks as a lack of resource problem, but instead as a lack of coordination between distributed entities.

“The root of the idea in this approach is that coordination would make the traditional interconnection network deadlock problem go away,” Gratz said. “As I recall, the basic idea came from teaching ECEN 350 where we talk a lot about pipelining. My thought was that in a pipelined processor there can be dependencies between stages but no deadlock occurs because the stages coordinate hand-offs from one to another. So why can't we do that in interconnection networks to handle the similar case of deadlocks?”

This solution has the potential to improve the battery life and reduce costs in smartphones and could also mean that less power is consumed by data centers such as those run by Facebook, Amazon or Google.