Dr. Daniel A. Jiménez, associate professor in the Department of Computer Science and Engineering at Texas A&M University, has been included in the High Performance Computer Architecture (HPCA) Hall of Fame for having seven papers in the IEEE International Symposium on High Performance Computer Architecture. There are 47 researchers from across the country who have this prestigious designation, for which one needs six or more papers published in the HCPA.
Jiménez has been a faculty member with since 2013. He received his bachelor's degree in computer science and systems design and his master's degree in computer science, both from the University of Texas at San Antonio. He received his Ph.D. in computer sciences from the University of Texas at Austin.
His five most recent HPCA papers are listed below.
— "Adaptive Placement and Migration Policy for an STT-RAM-Based Hybrid Cache," HPCA 2014, co-authored with Zhe Wang, Cong Xu, Guangyu Sun, and Yuan Xie. This paper proposes a hybrid last-level cache using spin torque transfer RAM alongside SRAM giving the capacity advantage of STT-RAM with the write-latency advantage of SRAM.
— "Improving Cache Performance Using Read-Write Partitioning," HPCA 2014, co-authored with Samira Khan, Alaa R. Alameldeen, Chris Wilkerson, and Onur Mutlu. This paper shows that distinguishing between clean and dirty blocks in cache sets enables a superior replacement policy, yielding improved performance. This paper was nominated for the Best Paper award.
— "Improving Multi-Core Performance Using Mixed-Cell Cache Architecture," HPCA 2013, co-authored with Samira Khan, Alaa Alameldeen, Chris Wilkerson, and Jaydeep Kulkarni. This paper introduces a last-level cache design that mixes large SRAM cells with small SRAM cells to provide improved capacity while maintaining reliability by keeping modified data in the large cells. The idea enables an improvement in both performance and power.
— "Decoupled Dynamic Cache Segmentation," HPCA 2012, HPCA 2012, co-authored with Samira M. Khan and Zhe Wang. This paper shows how to divide cache sets into two partitions, each of which is managed with a different replacement policy. It proposes a novel prediction mechanism to find the best size for a partition. The technique improves performance while allowing a reduced hardware budget.
— "A Decoupled KILO-Instruction Processor," HPCA 2006, co-authored with Miquel Pericàs, Ruben González, Adrian Cristal, and Mateo Valero. This paper shows how to combine many in-order components to build a large-instruction-window processor with low implementation cost. It introduces the concept of "execution locality" and exploits it to build a high-performance microprocessor.
Jiménez’s research interests include computer architecture and compliers. He is known for inventing the perceptron branch predictor, first published with co-author Calvin Lin in HPCA 2001. This method for predicting conditional branches is now used in machines made by AMD and Oracle. This semester, he is teaching CSCE 613: (Advanced) Operating Systems.
Yingying Tian is a current Ph.D. student at Texas A&M and Zhe Wang is a former Texas A&M Ph.D. student who is now working for Intel.
The IEEE Computer Society is a community for leaders in the technology sphere and the world's leading membership organization dedicated to computer science and technology. This organization sponsors more than 200 technical conferences and events each year, and the meeting this February was the 21st conference in the series.