• Associate Professor of Practice, Computer Science & Engineering
Michael Quinn

Educational Background

  • Master of Science Degree, Electrical Engineering, University of Southern California, 1978
  • Bachelor of Science Degree, Electrical Engineering, Drexel University, 1975

Industry Experience

  • • Pre-Silicon Functional Verification Leader of Intel Xeon and Itanium server processor designs
    • Responsible for developing overall verification strategy and associated innovations necessary for designing and validating complex and large designs

Selected Publications

  • "Zen and the Art of Alpha Validation" Co-authored for presentation at ICCD 1998.
  • "Functional Validation of a Multiple-Issue, Out-of-Order, Superscalar ALPHA Processor -- the ALPAH 21264 CPU Chip". Co-authored for presentation at DAC 1998.
  • "A Quality Design Process for Memory Modules". Paper presented at DECUS 1991 Fall Symposium.
  • "The High-Level Program Generator". Paper presented at 1982 Paris ATE Show.
  • "The Nibble-Mode Dynamic RAM". Workshop Chairman at 1982 Boston ATE Show.
  • "Dynamic Testing of Memory Arrays With ECC Logic". Paper presented at 1980 Cherry Hill ATE Show and at 1981 Wiesbaden ATE Show.
  • "Why A Memory Board Tester?". Paper presented at 1978 Cherry Hill ATE Show.