• Associate Professor
Sebastian Hoyos

Educational Background

  • Ph.D. University of Delaware, 2004
  • M.S. University of Delaware, 2002
  • B.S. Pontificia Universidad Javeriana, 2000

Research Interests

  • Novel design and implementation of embedded mixed-signal processing systems, techniques and algorithms with the objective of reducing power consumption and complexity, or enhancing performance, of high-speed and high dynamic range systems in biomedical sensing, wireline, and wireless communications.

    • Wireless and Wireline Communication Systems
    • Biomedical Sensing and Imaging
    • Joint Design of RF, Analog, Mixed-Signal and Digital Systems

Selected Publications

  • S. Kiran, S. Cai, Y. Luo, S. Hoyos, S. Palermo, “A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, pp. 1-13, Nov. 2018
  • J. Zhou, A. Tofighi, R. Gupta, L. Liu, Z. Wang, B. M. Sadler, J. Silva-Martinez, S. Hoyos, “Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 64, Issue 9, pp. 2495-2507, Sept. 2017
  • J. Zhou, S. Hoyos, and B. M. Sadler, “Asynchronous Compressed Beamformer for Portable Diagnostic Ultrasound Systems,” IEEE Trans. on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 61, No. 11, pp. 1791-1801, Nov. 2014.
  • J. Zhou, M. Ramirez, S. Palermo, S. Hoyos, “Digital-Assisted Asynchronous Compressive Sensing Front-End,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, No. 3, pp. 542-551, Sept. 2012.
  • X. Chen, E.A. Sobhy, Z. Yu, S. Hoyos, J. Silva-Martinez, S. Palermo, and B.M. Sadler, “A Sub-Nyquist Rate Compressive Sensing Data Acquisition Front-end,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, No. 3, pp. 482-492, Sept. 2012.
  • J. Zhou, M. Ramirez, S. Palermo, S. Hoyos, “Digital-Assisted Asynchronous Compressive Sensing Front-End,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, No. 3, pp. 542-551, Sept. 2012.
  • R. Ahmed, D.L. Aristizabal-Ramirez, and S. Hoyos, “Sensitivity Analysis of Continuous-Time Delta-Sigma ADCs to Out-of-Band Blockers in Future SAW-Less Multi-Standard Wireless Receivers,” IEEE Transactions on Circuits and Systems I, Vol. 59, No. 9, pp. 1894-1905, Sept. 2012
  • X. Chen, Z. Yu, S. Hoyos, B. M. Sadler, and J. Silva-Martinez, “A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing,” IEEE Transactions on Circuits and Systems I, Vol. 58, Issue 3, pp. 507-520, Mar. 2011.
  • S. Hoyos, S. Pentakota, Z. Yu, E. Sobhy, X. Chen, R. Saad, S. Palermo, and J. Silva-Martinez, “Clock-Jitter Tolerant Wideband Receivers: An Optimized Multi-Channel Filter-Bank Approach,” IEEE Transactions on Circuits and Systems I, Vol. 58, No. 2, pp. 253 – 263, Feb. 2011.
  • R. Saad and S. Hoyos, "Feed-Forward Spectral Shaping Technique for Clock-Jitter Induced Errors in Digital-to-Analog Converters," IET Electronics Letters, Vol 47, Issue 3, pp. 826-828, Feb. 2011.
  • E.A. Sobhy and S. Hoyos, “A Multiphase Multipath Technique With Digital Phase Shifters for Harmonic Distortion Cancellation,” IEEE Transactions on Circuits and Systems II, Vol. 57 , No. 12, pp. 921-925, Dec. 2010.
  • R. Saad and S. Hoyos, "Sensitivity of single-bit continuous-time analogue-to-digital converters to out-of-band blockers," IET Electronics Letters, Vol. 46, No. 12, pp. 826–828, June 2010.
  • K. Raviprakash, R. Saad, and S. Hoyos, “Reduced Area Discrete-Time Down-Sampling Filter Embedded with Windowed Integration Samplers,” IET Electronics Letters, Vol. 46, Issue 12, pp. 828–830, June 2010.
  • S. Hoyos, B. M. Sadler, and G. R. Arce, “Mono-bit digital receivers for ultra-wideband communications,” IEEE Transactions Letters on Wireless Communications, Vol. 4, No. 4, pp.1337-1344, July 2005
  • S. Hoyos, Y. Li, J. Bacca, and G. R. Arce, “Weighted median filters admitting complex-valued weights and their optimization,” IEEE Transactions on Signal Processing, Vol. 52, Issue 10, pp. 2776 – 2787, Oct. 2004.
  • S. Hoyos, J. A. Garcia, and G. R. Arce, “Mixed-signal equalization architectures for printed circuit boards,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 51, num. 2, pp. 264-274, Feb. 2004.