• Co-Director of Graduate Programs
  • Professor, Electrical & Computer Engineering
  • Affiliated Faculty, Computer Science & Engineering
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Jiang Hu

Educational Background

  • Ph.D., Electrical Engineering, University of Minnesota – 2001
  • M.S., Physics – 1997
  • B.S., Optical Engineering, Zhejiang University – 1990

Research Interests

    • Previous research: interconnect optimization, clock network synthesis, variation tolerant design, power efficient physical design and design for manufacturability
    • Current research: optimization for energy-efficient VLSI circuits, on-chip communication fabrics, dynamic power management, adaptive circuit design, interactions between physical design and system-level design, heuristics for large scale combinatorial optimization

Certifications & Memberships

  • Fellow, Institute of Electrical and Electronics Engineers (IEEE)

Awards & Honors

  • Best paper award, Association for Computing Machinery (ACM)/Institute of Electrical and Electronics Engineers (IEEE) Design Automation Conference – 2001
  • IBM Invention Achievement Award – 2003
  • Best paper award, Institute of Electrical and Electronics Engineers (IEEE)/Association for Computing Machinery (ACM) International Conference on Computer-Aided Design – 2011
  • General chair, Association for Computing Machinery (ACM) International Symposium on Physical Design – 2012
  • Associate editor, Institute of Electrical and Electronics Engineers (IEEE) Transactions on CAD – 2006-2011.

Selected Publications

  • C. J. Alpert, C. Chu, G. Gandham, M. Hrkic, J. Hu, C. Kashyap and S. T. Quay, “Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique,” IEEE Trans. Computer-Aided Design, Vol. 23, No. 1, pp. 136-141, January, 2004.
  • C. J. Alpert, J. Hu, S. S. Sapatnekar and P. G. Villarrubia, “A practical methodology for early buffer and wire resource allocation,” IEEE Trans. Computer-Aided Design, Vol. 22, No. 5, pp. 573-583, May, 2003.
  • J. Hu, C. J. Alpert, S. T. Quay and G. Gandham, “Buffer insertion with adaptive blockage avoidance”, IEEE Trans. Computer-Aided Design, Vol. 22, No. 4, pp. 492-498, April, 2003.
  • J. Hu and S. S. Sapatnekar, “A timing-constrained simultaneous global routing algorithm,” IEEE Trans. Computer-Aided Design, Vol. 21, No. 9, pp. 1025-1036, September 2002.
  • J. Hu and S. S. Sapatnekar, “Performance driven global routing through gradual refinement,” The VLSI Design Journal, Vol. 15, No. 3, pp. 595-604, 2002.
  • C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar and A. J. Sullivan, “Buffered Steiner trees for difficult instances,” IEEE Trans. Computer-Aided Design, Vol. 21, No. 1, pp. 3-14, January 2002.
  • J. Hu and S. S. Sapatnekar, “A survey on multi-net global routing for integrated circuits,” Integration: The VLSI Journal, Vol. 31, No. 1, pp. 1-49, November 2001. (Invited paper)
  • C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay and S. S. Sapatnekar, “Steiner tree optimization for buffers, blockages and bays,” IEEE Trans. Computer-Aided Design, Vol. 20, No. 4, pp. 556-562, April 2001.
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