- Associate Professor, Electrical & Computer Engineering
- Phone: 979-845-7486
- Email: gwanchoi@tamu.edu
- Office: WEB 333G
- Website: Research Website
Educational Background
- Ph.D., Electrical and Computer Engineering, University of Illinois at Urbana-Champaign – 1994
- M.S., Electrical and Computer Engineering, University of Illinois at Urbana-Champaign – 1989
- B.S., Electrical and Computer Engineering, University of Illinois at Urbana-Champaign – 1988
Research Interests
-
- Fault-tolerance
- Verification simulation
- High-performance VLSI circuits
- Radiation testing
- Design for dependability
- Software engineering
Awards & Honors
- National Science Foundations (NSF)career award, 1997
Selected Publications
- G. Choi, R. Iyer, V. Carreno, Simulated Fault Injection: A Methodology to Evaluate Fault Tolerant Microprocessor Architectures, IEEE Transaction on Reliability Special Issue on Experimental Evaluation, Vol, 39, No. 4, pp. 486-491, October 1990.
- G. Choi, R. Iyer, R. Saleh, V. Carreno, A Fault Behavior Model For and Avionic Microprocessor, Dependable Computing, Editors: A. Avizienis, J. Laprie, pp 177-195, Springer-Verlag, 1990.
- G. Choi, R. Iyer, FOCUS: An Experimental Environment for Fault Sensitivity Analysis, IEEE Transaction on Computers, Vol. 41, No. 12, pp.1515-1526, December 1992.
- H. Cha, E. Rudnick, J. Patel, R. Iyer, G. Choi, A Fast and Accurate Gate-Level Transient Fault Simulation Environment, IEEE Transaction on Computer, Vol. 45, No. 11, pp. 1248-1256, November 1996.
- S. Hwang, G. Choi, Selective-Set-Invalidation(SSI) for Soft-Error-Resilient Cache Architecture, ACM SIGARCH, Computer Architecture News, pp. 32-38, June, 1999.
- S. Hwang, G. Choi, :RTMS: A Reliability Testing Environment for Off-The-Shelf Memory- Subsystems, IEEE Design & Test, June, 1999.
- B. Min, G. Choi, Verification Simulation Acceleration Using Code-Perturbation, Journal of Electronic Testing and Testing Automation, JETTA, Volume 16, Issue 1, Feb 2000.
- Rohit Singhal*, Gwan Choi, Rabi N. Mahapatra, Data Handling Limits of On-Chip Interconnects, IEEE Transactions on Very Large Scale Integration Systems 16(6): 707-713 (2008).
- Garg, Jayakumar*, Khatri, Choi, Circuit-level Design Approaches for Radiation-hard Digital Electronics, IEEE transactions on very large scale integration (VLSI) systems, ISSN 1063-8210.
- Wang, Weihuang; Kim, Euncheol; Gunnam, Kiran K.; Choi, Gwan S., Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels, Journal of Low Power Electronics, Volume 5, Number 3, October 2009 , pp. 303-312(10).