Jiang Hu

Professor

Co-Director of Graduate Programs

Hu

Office: WEB 333L
Phone: 979.847.8768
Fax: 979.845.2630
Email: jianghu@tamu.edu

Research Website
Google Scholar Profile

Research Interests

  • Previous research: interconnect optimization, clock network synthesis, variation tolerant design, power efficient physical design and design for manufacturability.
  • Current research: optimization for energy-efficient VLSI circuits, on-chip communication fabrics, dynamic power management, adaptive circuit design, interactions between physical design and system-level design, heuristics for large scale combinatorial optimization.

Awards & Honors

  • IEEE Fellow
  • Best paper award at the ACM/IEEE Design Automation Conference in 2001
  • IBM Invention Achievement Award in 2003
  • Best paper award at the IEEE/ACM International Conference on Computer-Aided Design in 2011
  • Served as technical program committee members for DAC, ICCAD, ISPD, ISQED, ICCD, DATE, ISCAS, ASP-DAC and ISLPED
  • General chair for the 2012 ACM International Symposium on Physical Design.
  • Associate editor of IEEE Transactions on CAD 2006-2011.

Education

  • B.S. degree in optical engineering from Zhejiang University (China) in 1990
  • M.S. degree in physics in 1997
  • Ph.D. degree in electrical engineering from the University of Minnesota in 2001.

Selected Publications

H. Hou, J. Hu and S. S. Sapatnekar, “NonHanan routing,” IEEE Trans. Computer-Aided Design, Vol. 18, No. 4, pp. 436-444, April 1999.

J. Hu and S. S. Sapatnekar, “Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher order AWE model,” IEEE Trans.

C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay and S. S. Sapatnekar, “Steiner tree optimization for buffers, blockages and bays,” IEEE Trans. Computer-Aided Design, Vol. 20, No. 4, pp. 556-562, April 2001.

J. Hu and S. S. Sapatnekar, “A survey on multi-net global routing for integrated circuits,” Integration: The VLSI Journal, Vol. 31, No. 1, pp. 1-49, November 2001. (Invited paper)

C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar and A. J. Sullivan, “Buffered Steiner trees for difficult instances,” IEEE Trans. Computer-Aided Design, Vol. 21, No. 1, pp. 3-14, January 2002.

J. Hu and S. S. Sapatnekar, “Performance driven global routing through gradual refinement,” The VLSI Design Journal, Vol. 15, No. 3, pp. 595-604, 2002.

J. Hu and S. S. Sapatnekar, “A timing-constrained simultaneous global routing algorithm,” IEEE Trans. Computer-Aided Design, Vol. 21, No. 9, pp. 1025-1036, September 2002.

J. Hu, C. J. Alpert, S. T. Quay and G. Gandham, “Buffer insertion with adaptive blockage avoidance”, IEEE Trans. Computer-Aided Design, Vol. 22, No. 4, pp. 492-498, April, 2003.

C. J. Alpert, J. Hu, S. S. Sapatnekar and P. G. Villarrubia, “A practical methodology for early buffer and wire resource allocation,” IEEE Trans. Computer-Aided Design, Vol. 22, No. 5, pp. 573-583, May, 2003.

C. J. Alpert, C. Chu, G. Gandham, M. Hrkic, J. Hu, C. Kashyap and S. T. Quay, “Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique,” IEEE Trans. Computer-Aided Design, Vol. 23, No. 1, pp. 136-141, January, 2004.