Paul Gratz

Associate Professor

Gratz

Office: WEB 333M
Phone: 979.488.4551
Fax: 979.845.2630
Email: pgratz@tamu.edu

Research Website
Google Scholar Profile

Research Interests

  • Security, power, reliability and performance in multicore and distributed computer architectures.
  • Processor memory systems.
  • On-chip interconnection networks.

Education

  • PhD in Electrical and Computer Engineering from the University of Texas at Austin, December 2008.

Selected Publications

“Bidirectional Interconnect Design for Low Latency High Bandwidth NoC”, R. Kumar, H. Deshpande, G. Choi, A. Sprintson, P. Gratz , 2013 International Conference on IC Design and Technology, May 2013. (to appear)

“Dynamic Voltage and Frequency Scaling for Shared Resources in Multicore Processor Designs”, X. Chen, Z. Xu, H. Kim, P. Gratz, J. Hu, M. Kishinevsky, U. Ogras and R. Ayoub. The 50th ACM/EDAC/IEEE The Design Automation Conference (DAC), June 2013. (to appear)

“GCA:Global Congestion Awareness for Load Balance in Networks-on-Chip”, M. Ramakrishna, P. V. Gratz and A. Sprintson. The Seventh ACM/IEEE International Symposium on Networks-on-Chip (NOCS), April 2013. (to appear)

“LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip for Future Parallel Architectures”, C. Li, M. Browning, P. V. Gratz and S. Palermo. The Seventh ACM/IEEE International Symposium on Networks-on-Chip (NOCS), April 2013. (to appear) (poster and presentation)

“NOCS Special Section: Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip”, H. Kim, B. Grot, P. V. Gratz, D. Jiminez, IEEE Transactions on Computers, no.99, pp.1 (to appear)

“WaveSync: Low-Latency Source Synchronous Bypass Network-On-Chip Architecture”, Y. Yang, R. Kumar, G. Choi and P. V. Gratz, The 30th IEEE International Conference on Computer Design (ICCD), Oct. 2012.

“LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip for Future Parallel Architectures”, C. Li, M. Browning, P. V. Gratz and S. Palermo. The 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), Sept. 2012. (Poster and Abstract)

“Energy-efficient Optical Broadcast for Nanophotonic Networks-on-Chip”, C. Li, M. Browning, P. V. Gratz and S. Palermo. The 2012 IEEE Optical Interconnects Conference (OIC), May 2012.

“In-Network Monitoring and Control Policy for DVFS of CMP Networks-On-Chip and Last Level Caches”, Xi Chen, Zheng Xu, Hyungjun Kim, Paul Gratz, Jiang Hu, Michael Kishinevsky and Umit Ogras. The Sixth ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2012. (Nominated for Best Paper) pdf, bibtex.

“Exploiting Path Diversity for Low-Latency and High-Bandwidth with the Dual-path NoC Router,” Y. S. Yang, H. Deshpande, G. Choi and P. V. Gratz. The 2012 IEEE International Symposium on Circuits and Systems (ISCAS), May 2012. pdf, bibtex.