High Performance Computing Architectures and Applications
Computer Architecture, Hardware Verification, Project Management
20 years of service at Intel in positions ranging from individual technical contributor to Senior Director in Server Development Group. Worked on 8 generations of CPU’s at Intel; most recently managed the Design and Execution of Knights Landing: 2015 2nd Generation Xeon Phi Product
Awards & Honors
- 32 Intel Department and Division awards for individual and team achievements, 1995.
- Repeat annual recognition in Top-800 Leaders in Intel Corporation, 2010-2013.
- CSE Undergraduate Faculty Teaching Excellence Award, TAMU-Department, 2015.
- TAMU Professor of Practice Instructional Grant Award, 2015.
- Ph.D. Computer Engineering, University of Louisiana, Lafayette, Louisiana, 1993
- M.S. Electrical and Computer Engineering, University of Louisiana, Lafayette, Louisiana, 1989
- B.S. Electronics & Communication, Kamla Nehru Institute of Technology, Sultanpur, India, 1987
A. Tyagi and M.A. Bayoumi, “Image Segmentation on a 2D Array by a Directed Split and Merge Procedure,” IEEE Transactions on Signal Processing, Vol. 40, No. 2, November 1992, pp 2804- 2813.
A. Tyagi and M.A. Bayoumi, “Defect Clustering Viewed Through Generalized Poisson Distribution,” IEEE Transactions on Semiconductor Manufacturing, Vol. 5, No. 3, August 1992, pp. 196-206.
M.K. Kidambi, A. Tyagi, M.R. Madani, and M.A. Bayoumi, "Three-Dimensional Defect Sensitivity Modeling for Open Circuits in ULSI Structures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 4, April 1998, pp. 366-371.
A. Tyagi and M.A. Bayoumi, “The Nature of Defect Patterns on Integrated-Circuit Wafer Maps,” IEEE Transactions on Reliability, March 1994, pp. 22-29.
S. Popli, M.A. Bayoumi and A. Tyagi, “A Reconfigurable Technique for Reliable VLSI DSP Array Processors,“ Journal of Circuits, Systems, and Computers, Vol. 4, No. 3, March 1992, pp. 281- 304.