- Computer architecture
- Power efficient systems
- Parallel/distributed systems
- Cluster computing
- Performance evaluation
- Fault-tolerant computing
Awards & Honors
- NSF Early CAREER Award, 2009
- Ph.D. Computer Science and Engineering, Pennsylvania State University, 2003
- M.S. Computer Science and Engineering, Pohang University of Science and Technology, 1994
- B.S. Computer Science, Korea Advanced Institute of Science and Technology, 1992
L. Wang, P. Kumar, K. H. Yum and E. J. Kim, "APCR: An Adaptive Physical Channel Regulator for On-Chip Interconnects," International Conference on Parallel Architectures and Compilation Techniques (PACT), Minneapolis, MN, September 2012.
H. Jang, B. S. An, N. Kulkarni, K. H. Yum and E. J. Kim, "A Hybrid Buffer Design with STT-MRAM for On-Chip Interconnects," ACM/IEEE International Symposium on Networks-on-Chip (NOCS), Copenhagen, Denmark, May 2012.
B. S. An, M. Lee, K. H. Yum and E. J. Kim, "Efficient Data Packet Compression for Cache Coherent Multiprocessor Systems," iData Compression Conference (DCC), Snowbird, Utah, April 2012.
Y. Jin, E. J. Kim and T. M. Pinkston, "Communication-Aware Globally-Coordinated On-Chip Networks," in IEEE Transactions on Parallel and Distributed Systems (TPDS), May 2011.
M. Lee, M. Ahn and E. J. Kim, "Fast Secure Communications in Shared Memory Multiprocessor Systems," IEEE Transactions on Parallel and Distributed Systems (TPDS), April 2011.
Minseon Ahn and E. J. Kim, "Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks," in International Symposium on Microarchitecture (MICRO-43), Atlanta, Georgia, December 2010.