- Integrated circuit test
- Defect-based test
- Delay test
- IDDQ test
- Fault diagnosis
- Realistic fault modeling
- Parametric and functional yield prediction
Awards & Honors
- ACM Distinguished Scientist, 2014
- Charles W. Crawford Service Award, 2009-2010
- E. D. Brockett Professorship, 2007-2008
- Lockheed Martin Aeronautics Company Excellence in Engineering Teaching Award, 2006
- Texas A&M University College of Engineering Fellow, Texas A&M, 2006-2007
- AMD Fellow, College of Engineering, Texas A&M, 2002-2003
- TEES Fellow, College of Engineering, Texas A&M, 1998-1999
- Ph.D., Computer Science, Carnegie Mellon University, 1986
- M.S., Computer Science, Carnegie Mellon University, 1984
- B.S., Engineering (Honors), California Institute of Technology, 1979
Z. Wang and D. M. H. Walker, “Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric,” IEEE VLSI Test Symposium, Santa Cruz, CA, May 2009.
Z. Wang and D. M. H. Walker, “Dynamic Compaction for High Quality Delay Test,” IEEE VLSI Test Symposium, Rancho Bernardo, CA, May 2008, paper 8.1.
S. Sabade and D. M. H. Walker, “Estimation of Fault-Free Leakage Using Wafer-Level Spatial Information,” IEEE Transactions on VLSI Systems, vol. 14, no. 1, January 2006, pp. 91-94.
X. Lu, Z. Li, W. Qiu, D. M. H. Walker and W. Shi, “Longest Path Selection for Delay Test under Process Variation,” IEEE Transactions on Computer-Aided Design, vol. 24, no. 12, December 2005, pp. 1924-1929.