Daniel A. Jiménez

Professor

Image of Daniel Jimenez

Office: 509D HRBB
Phone: 979.845.2434
Email

Personal Website
Curriculum Vitae
Google Scholar Profile

Education

  • Ph.D. in Computer Sciences, Department of Computer Sciences, The University of Texas at Austin
  • M.S. in Computer Science, Division of Computer Science, The University of Texas at San Antonio
  • B.S. in Computer Science and Systems Design, Division of Mathematics, Computer Science, and Statistics, The University of Texas at San Antonio

Selected Publications

Zhe Wang, Samira M. Khan, Daniel A. Jiménez, Improving Writeback Efficiency with Decoupled Last Write Prediction, Proceedings of the 39th International Symposium on Computer Architecture (ISCA-39), Portland, Oregon, June 2012

Samira M. Khan, Zhe Wang, Daniel A. Jiménez, Decoupled Dynamic Cache Segmentation, Proceedings of the 18th International Symposium on High Performance Computer Architecture (HPCA-18), New Orleans, Louisiana, February 2012

Zhe Wang, Daniel A. Jiménez, Program Interferometry Proceedings of the 2011 International IEEE International Symposium on Workload Characterization (IISWC), pp. 172--183, Austin, Texas, November 2011

Daniel A. Jiménez, An Optimized Scaled Neural Branch Predictor, Proceedings of the 2011 IEEE International Conference on Computer Design (ICCD), Amherst, Massachusetts, October 2011

Samira M. Khan, Yingying Tian, Daniel A. Jiménez, Dead Block Replacement and Bypass with a Sampling Predictor, Proceedings of the 43rd International Symposium on Microarchitecture (MICRO-43), Atlanta, Georgia, December 2010

Samira Khan, Daniel A. Jiménez, Doug Burger and Babak Falsafi, Using Dead Blocks as a Virtual Victim Cache, Proceedings of the 2010 International Conference on Parallel Architectures and Compilation Technologies (PACT-2010), Vienna, Austria, September, 2010

Renée St. Amant, Daniel A. Jiménez and Doug Burger, Low-Power, High-Performance Analog Neural Branch Prediction, Proceedings of the 41st Annual International Symposium on Microarchitecture (MICRO-41), Lake Como, Italy, November 2008.

Miquel Pericàs, Adrian Cristal, Francisco J. Cazorla, Ruben González, Alex Veidenbaum, Daniel A. Jiménez and Mateo Valero, A Two-Level Load/Store Queue Based on Execution Locality, Proceedings of the 35th International Symposium on Computer Architecture (ISCA-35), June 2008

Daniel A. Jiménez, Piecewise Linear Branch Prediction, Proceedings of the 32nd International Symposium on Computer Architecture (ISCA-32), June 2005

Daniel A. Jiménez, Code Placement for Improving Dynamic Branch Prediction Accuracy, Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation (PLDI), June, 2005